ASIC Engineer, Design Verification
Meta

Job Info

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Meta's data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

ASIC Engineer, Design Verification Responsibilities:

• Lead the DV effort of complex Compute IP's, from start to finish
• Define and implement complex Compute IP verification plans, architect & build reusable test benches, coordinate technical work across multiple sub-blocks
• Work closely with the design, performance/modeling and emulation teams to identify/define microarchitecture performance KPIs, setup testbenches to achieve the desired goals
• Contribute to the development of CPU ISA test generation tools
• Collaborate with the team to build comprehensive & reusable checking methodology for CPU/GPU like IP (instruction accurate models, memory consistency & coherence models etc.)
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team Develop and drive continuous Design Verification improvements

Minimum Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
• Strong background in Computer Architecture, memory & cache coherency, data consistency, CPU fetch/decode/load-store/cache blocks
• 10+ years experience in complex CPU/GPU verification, proven track record of 'first-pass success in similar environments
• 10+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
• Experience with verification techniques beyond simulation - like assertions, formal, emulation and software-driven verification
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
• Experience in architecting and implementing Design Verification infrastructure

Preferred Qualifications:

• Experience with verification of ARM/RISC-V based CPUs, GPUs and subsystems used for general purpose compute
• Experience with Design verification of Data-center applications for AI/ML
• Experience in development of UVM based verification environments from scratch
• Experience with revision control systems like Mercurial(Hg), Git or SVN
• Experience working across and building relationships with cross-functional design, model and emulation teams

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